Electrically alterable non-volatile memory with n-bits per cell

ABSTRACT

A multi-bit memory device with a memory cell means for storing input information for an indefinite period of time. The multi-bit memory means stores information in up to K n  memory states (K n &gt;1). A memory cell programming means and comparator means is also included. The present multi-bit memory device also includes a voltage divider arrangement with pull-up devices in a memory array to provide stable and accurate reference voltages over process, temperature, and voltage variations.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 08/071,816, filed Jun. 4, 1993 entitled“Electrically Alterable Non-Volatile Memory with N-Bits Per MemoryCell,” which is a continuation of U.S. patent application Ser. No.07/652,878, filed Feb. 8, 1991 (now U.S. Pat. No. 5,218,569) entitled“Electrically Alterable Non-Volatile Memory with N-Bits Per Cell.”

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to non-volatile memory (NVM) devices; and,more particularly, is concerned with an apparatus and method forproviding a multi-level NVM device with stable reference voltages.

[0004] 2. Description of the Background Art

[0005] In conventional single-bit per cell memory devices, the memorycell assumes one of two information storage states, either an “on” stateor an “off” state. This combination of either “on” or “off” defines onebit of information. As a result, a memory device which can store n-bitsof data requires n separate memory cells.

[0006] Increasing the number of bits which can be stored in a single-bitper cell memory device relies upon increasing the number of memory cellson a one-for-one basis with the number of bits of data to be stored.Methods for increasing the number of memory bits in a single memorydevice have relied upon the following advanced manufacturing techniques:manufacture larger die which contain more memory cells; or use improvedlithography techniques to build smaller memory cells and allow morememory cells to be placed in a given area on a single chip.

[0007] An alternative approach to the single-bit per cell approachinvolves storing multiple-bits of data in a single memory cell. Previousapproaches to implementing multiple-bit per cell non-volatile memorydevices have only involved mask programmable read only memories (ROMs).In one of these approaches, the channel width and/or length of thememory cell is varied such that 2^(n) different conductivity values areobtained which correspond to 2^(n) different states corresponding ton-bits of data which can be stored on a single memory cell. In anotherapproach, the ion implant for the threshold voltage is varied such thatthe memory cell will have 2^(n) different voltage thresholds (Vt)corresponding to 2^(n) different conductance levels corresponding to2^(n) different states corresponding to n-bits of data which can bestored on a single memory cell. Examples of memory devices of thesetypes are described in U.S. Pat. No. 4,192,014 by Craycraft, U.S. Pat.No. 4,586,163 by Koike, U.S. Pat. No. 4,287,570 by Stark, U.S. Pat. No.4,327,424 by Wu, and U.S. Pat. No. 4,847,808 by Kobatake.

[0008] Single-bit per cell read-only-memory devices are only required tosense, or read, two different levels or states per cell, consequentlythey have need for only one voltage reference. Sensing schemes formulti-level memory devices are more complex and require 2^(n)−1 voltagereferences. Examples of such multiple state sensing schemes for ROMs aredescribed in U.S. Pat. No. 4,449,203 by Adlhoch, U.S. Pat. No. 4,495,602by Shepard, U.S. Pat. No. 4,503,578 by Iwahashi, and U.S. Pat. No.4,653,023 by Suzuki. A limitation with the conventional sensing schemesis often inaccurate and unstable reference voltage levels. Theconventional sensing schemes have reference voltage levels which cannotaccurately track bit line voltage levels through process, temperature,and voltage variations.

[0009] These approaches to a multi-bit ROM commonly have one of 2^(n)different conductivity levels of each memory cell being determinedduring the manufacturing process by means of a customized mask that isvalid for only one data pattern. Thus, for storing n different datainformation patterns, a minimum of n different masks need to be producedand incorporated into a manufacturing process. Each time a datainformation pattern needs to be changed a new mask must be created and anew batch of semiconductor wafers processed. This dramatically increasesthe time between a data pattern change and the availability of a memoryproduct programmed with that new data pattern.

[0010] Prior art electrically alterable multiple-bit per cell memoryapproaches store multiple levels of charge on a capacitive storageelement, such as is found in a conventional dynamic random access memory(DRAM) or a charge coupled device (CCD). Such approaches are describedin U.S. Pat. No. 4,139,910 by Anantha, U.S. Pat. No. 4,306,300 byTerman, U.S. Pat. No. 4,661,929 by Aoki, U.S. Pat. No. 4,709,350 byNakagome, and U.S. Pat. No. 4,771,404 by Mano. All of these approachesuse volatile storage, that is, the charge levels are not permanentlystored. They provide 2^(n) different volatile charge levels on acapacitor to define 2^(n) different states corresponding to n-bits ofdata per memory cell. All of these approaches have the commoncharacteristic that whatever information is stored on such a memory cellis volatile because such a cell loses its data whenever power isremoved. Furthermore, these types of memory cells must be periodicallyrefreshed as they have a tendency to lose charge over time even whenpower is maintained.

[0011] It would be advantageous to develop a multi-bit semiconductormemory cell that has the non-volatile characteristic of a maskprogrammable read-only-memory (ROM) and the electrically alterablecharacteristic of a multi-bit per cell DRAM. These characteristicscombined in a single cell would provide a multi-bit per cellelectrically alterable non-volatile memory (EANVM) capable of storingK^(n) bits of data, where “K” is the base of the numbering system beingused and “n” is the number of bits to be stored in each memory cell.Additionally, it would be advantageous if the EANVM described above wasfully compatible with conventional industry standard deviceprogrammers/erasers and programming/erasing algorithms such that a usercan program/erase the multi-bit per cell memory in a manner identical tothat used for current single-bit per cell memory devices.

SUMMARY OF THE INVENTION

[0012] The present invention provides a multi-level electricallyalterable non-volatile memory (EANVM) device, wherein some or all of thestorage locations have more than two distinct states and such states arecompared to stable reference voltages. The stable reference voltages aregenerated by way of cells made during the same (or similar) processsteps as the memory device.

[0013] In a specific embodiment, the present invention provides amulti-level memory device. The present multi-level memory deviceincludes a multi-level cell means for storing input information for anindefinite period of time as a discrete state of the multi-level cellmeans. The multi-level cell means stores information in K^(n) memorystates, where K is a base of a predetermined number system, n is anumber of bits stored per cell, and K^(n)>2. The present multi-levelmemory device also includes a memory cell programming means forprogramming the multi-level cell means to a state corresponding to theinput information. A comparator means for comparing the memory state ofthe multi-level cell means with the input information is also included.The input information corresponds to one of a plurality of referencevoltages. The present comparator means further generates a controlsignal indicative of the memory state as compared to the inputinformation.

[0014] An alternative specific embodiment also provides a multi-levelmemory device. The-present multi-level memory device includes amulti-level cell means for storing input information for an indefiniteperiod of time as a discrete state of the multi-level cell means. Themulti-level cell means stores information in K^(n) memory states, whereK is a base of a predetermined number system, n is a number of bitsstored per cell, and K^(n)>2. A memory cell programming means forprogramming the multi-level cell means to a state corresponding to theinput information is also included. The present multi-level memorydevice further includes a comparator means for comparing the memorystate of the multi-level cell means with the input information. Theinput information corresponds to one of a plurality of referencevoltages. The present comparator means further generates a controlsignal indicative of the memory state as compared to the inputinformation. A reference voltage means for defining the plurality ofreference voltages is also included. The present reference voltage meansis operably coupled to the comparator means.

[0015] In an alternative specific embodiment, the present inventionprovides an integrated circuit with a plurality of multi-level cells.The present integrated circuit includes a multi-level memory cell forstoring input information for an indefinite period of time as a discretestate of said multi-level memory cell. The multi-level memory cellstores information in K^(n) memory states, where K is a base of apredetermined number system and n is a number of bits stored permulti-level memory cell, wherein K^(n)>2. The present integrated circuitalso includes a memory cell programming circuit for programming themulti-level memory cell to a memory state corresponding to the inputinformation. A comparator for comparing the memory state of themulti-level memory cell with the input information is also included. Theinput information corresponds to one of a plurality of referencevoltages. The comparator means further generates a control signalindicative of the memory state as compared to the input information. Thepresent integrated circuit also includes a reference voltage cell forproviding the one plurality of reference voltages. The reference voltagecell is operably coupled to the comparator. The multi-level memory cellis defined by one of the plurality of multi-level cells and thereference voltage cell is defined by another of the plurality ofmulti-level cells.

[0016] A further embodiment provides an integrated circuit device with aplurality of multi-level cells. The plurality of multi-level cellsdefines a multi-level memory cell and a reference voltage cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and form apart of this specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

[0018]FIG. 1 is a generic schematic representation of a non-volatilefloating gate memory cell.

[0019]FIG. 2 is a block diagram of a prior art single-bit memory system.

[0020]FIG. 3 is a timing diagram of the voltage threshold of a prior artsingle-bit per cell EANVM system being programmed from an erased “1”state to a programmed “0”.

[0021]FIG. 4 is a timing diagram of the bit line voltage of a priorsingle-bit per cell EANVM during a read operation. It illustrateswaveform levels for both the programmed and erased conditions.

[0022]FIG. 5 is a block diagram of an M×N memory array implementing amulti-bit per cell EANVM system.

[0023]FIG. 6 is a block diagram for reading a multi-bit per cell EANVMsystem.

[0024]FIG. 7 shows the bit line voltage during a read cycle as afunction of time for a 2-bit per cell EANVM which has been programmed toone of four possible states, (0,0), (1,0), (0,1) and the fully erasedcondition (1,1). Four separate voltage levels are represented on thisfigure, each representing one of the four possible states. Only one ofthese would be present for any given read operation.

[0025]FIG. 9 is a timing diagram which illustrates the voltage thresholdof a 2-bit per cell EANVM being erased from a fully programmed (0,0)state to one of the other three possible states.

[0026]FIG. 8 is a block diagram of a multi-bit per cell system combiningprogram/verify and read circuitry.

[0027]FIG. 9 is a timing diagram for the voltage threshold for a 2-bitper cell EANVM being programmed from a fully erased (1,1) state to oneof the other three possible states.

[0028]FIG. 11 is a timing diagram illustrating the voltage threshold ofa 2-bit per cell EANVM during a program/verify cycle using fixed widthprogram pulses.

[0029]FIG. 12 is a timing diagram illustrating the bit line voltage of a2-bit per cell EANVM during a program/verify process which uses fixedwidth program pulses.

[0030]FIG. 13 is a timing diagram illustrating the voltage threshold ofa 2-bit per cell EANVM during a program/verify cycle using variablewidth program pulses.

[0031]FIG. 14 is a timing diagram illustrating the bit line voltage of a2-bit per cell EANVM during a program/verify process which uses variablewidth program pulses.

[0032]FIG. 15 is a simplified diagram of voltages for a 2-bit per memorycell according to the present invention.

[0033]FIG. 16 is a simplified voltage generator circuit diagram of avoltage divider arrangement for generating multiple reference voltagesaccording to the present invention.

[0034]FIG. 17 illustrates the reference voltages of FIG. 16 according tothe present invention.

[0035]FIG. 18 is a simplified voltage generator circuit diagram for anarray showing reference voltage columns connected to pull-up devicesaccording to the present invention.

[0036]FIG. 19 is a simplified voltage generator circuit diagram forobtaining reference voltages with use of pull-up devices and a voltagedivider according to a preferred embodiment of the present invention.

[0037]FIG. 20 is a simplified diagram of a voltage generator circuitaccording to an alternative embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0038] Reference will now be made in detail to the specific embodimentsof the invention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thespecific embodiments, it will be understood that they are not intendedto limit the invention to those embodiments. On the contrary, theinvention is intended to cover various alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims.

[0039] In general, the invention described here allows n-bits ofinformation to be stored on and read from an Electrically AlterableNon-Volatile Memory (EANVM). This is accomplished by electricallyvarying the conductivity of the channel of a floating gate FET to bewithin any one of K^(n) conductivity ranges where “K” represents thebase of the numbering system being employed (in a binary system, “K”equals 2). The conductivity range is then sensed and encoded. This formsthe basis of an n-bit EANVM memory cell. The floating gate FETconductivity is electrically modified by using conventional externalprogramming hardware and algorithms which supply conventional signalsand voltages to the EANVM memory device.

[0040] These external signals and voltages are then modified internal tothe device to provide an internally controlled program/verify cyclewhich incrementally stores electrons on the floating gate until thedesired conductivity range is achieved. For the purpose of illustration,the n-bit per cell descriptions will assume a binary system which stores2-bits per memory cell.

[0041] I. PRIOR ART SINGLE-BIT EANVM DEVICES

[0042]FIG. 1 is a generic schematic representation of a non-volatilefloating gate memory cell 10. It is not intended that this schematicdrawing is in any way indicative of the device structure. It is used toillustrate the fact that this invention refers to an FET memory cellwhich uses an electrically isolated, or floating, gate 14 to storecharged particles for the purpose of altering the voltage threshold andhence channel conductivity of the FET memory cell 10.

[0043] The FET memory cell 10 includes a-control gate 12 which is usedeither to select the memory cell for reading or is used to causeelectrons to be injected onto the floating gate 14 during theprogramming process. Floating gate 14 is an electrically isolatedstructure which can indefinitely store electrons. The presence orabsence of electrons on floating gate 14 alters the voltage threshold ofthe memory cell 10 and as a result alters the conductivity of itschannel region. A drain region 16 of the FET is coupled to a sourceregion 18 by a channel region 19. When the floating gate 14 is fullyerased and the control gate 12 has been selected, the channel region 19is in the fully “on”, or high conductivity, state. When the floatinggate 14 is fully programmed the channel region 19 is in the fully “off”,or low conductivity state.

[0044]FIG. 2 is a block diagram of a prior art conventional single-bitEANVM memory system 30. The memory system 30 stores a single bit ofinformation in an EANVM cell 32. The cell 32, as described in FIG. 1, isselected for reading or writing when a row, or word, select signal isapplied to a control gate terminal 34. A source terminal 36 for the FETof the cell 32 is connected to a reference ground potential. A drainterminal 38 is connected through a pull-up device 39 to a voltagesVpull-up at a terminal 40. Terminal 38 serves as the output terminal ofthe cell 32. When the cell 32 stores a “1” bit, the channel of the FETis in a low conductivity, or high impedance, state so that the voltageat terminal 38 is pulled-up to the voltage level Vpull-up on terminal40. When the cell 32 stores a “1” bit, the channel of the FET is in ahigh conductivity, or low impedance, state so that the voltage atterminal 38 is pulled-down by the ground potential at terminal 36.

[0045] For reading the value of the single-bit stored in the cell 32, asense amplifier 42 compares the voltage at terminal 38 with a referencevoltage Vref at terminal 43. If a “0” is stored on the EANVM cell 32,the cell will be in a low conductivity state and as a result the voltageat terminal 38 is above the reference voltage at terminal 43. For a “0”stored in the cell 32, the output terminal 44 of the sense amplifier 42will be a low voltage which will be transmitted through an output buffer46 to a terminal 48 and then coupled to the I/O terminal 50 as a logical“0”. If a “1” is stored on the EANVM cell 32, the cell is in a highconductivity state and as a result the voltage at terminal 38 is belowthe reference voltage at terminal 43. The output of the sense amplifier42 will be a high voltage which will be transmitted to the I/O terminal50 as a logical “1”.

[0046] For writing the value of an information bit stored in the cell32, it is assumed that the cell 32 is in the erased, or fully “on”,state which corresponds to a logical “1”. The I/O terminal 50 isconnected to the input terminal of an input latch/buffer 52. The outputof the input latch/buffer 52 is connected to an enable/disable terminal54 of a program voltage switch 56. The program voltage switch 56provides a bit-line program voltage on a signal line 58 connected toterminal 38. Another output from the program voltage switch 56 is theword line program voltage on a signal line 62, which is connected to thecontrol gate 34 of the EANVM cell 32. When a logical “0” is present atterminal 54 of the program voltage switch 56 from the output of InputLatch/Buffer 52 and when the program voltage switch 56 is activated by aprogram pulse on a signal line 62 from a program pulse 66, activated bya PGM/Write signal, the program voltage switch 56 provides the ProgramVoltage Vpp from a terminal 68 to the control gate 34 of the EANVM cell32. The program voltage switch 56 also biases the drain of the EANVMcell 32 to a voltage, typically between 8 to 9 volts, and the gate ofthe EANVM cell 32 to the program voltage Vpp, typically 12 volts. Underthese conditions, electrons are injected onto the floating gate by aphenomenon known as hot electron injection. This programming procedureraises the voltage threshold of the EANVM cell which increases itssource-drain impedance. This continues until the FET memory cell 32 iseffectively turned off, which corresponds to a “0” state. When a “1”ispresent on terminal 54 from the output of the Input Latch/Buffer 52 andwhen the PGM/Write is enabled, the signal line 58 is driven low andprogramming is inhibited and the “1”, or erased, state is maintained.

[0047]FIG. 3 is a timing diagram of a prior-art single-bit EANVM cell32, as described in connection with FIG. 2. The timing diagram shows thechange in voltage threshold of the EANVM cell 32, as controlled by theword line and bit line programming voltages, which are illustrativelyshown as a single signal and which are both controlled by the PGM/Writesignal. The memory cell is being programmed from the fully-erased “1”state to the fully programmed “0” state. For the duration of thePGM/Write pulse, the bit and word line program voltages, which need notbe the same, are respectively applied to the source connected to the bitline 38 and to the control gate 34 of the memory cell 32. As electronsare injected onto the floating gate, the voltage threshold of the memorycell begins to increase. Once the voltage threshold has been increasedbeyond a specific threshold value as indicated by the dashed horizontalline, the memory cell 32 is programmed to a “0” state.

[0048] Note that Fowler-Nordheim tunnelling can also be used instead ofhot electron injection to place electrons on the floating gate. Themulti-bit EANVM device described here functions with either memory cellprogramming technique. The prior art programming algorithms and circuitsfor either type of programming are designed to program a single-bit cellwith as much margin as possible in as short a time as possible. For asingle-bit memory cell, margin is defined as the additional voltagethreshold needed to insure that the programmed cell will retain itsstored value over time.

[0049]FIG. 4 is a timing diagram showing the bit line voltage atterminal 38 as a function of time during a memory read operation. Inthis example, prior to time t1 the bit line is charged to the Vpull-upcondition. Note that it is also possible that the bit line may start atany other voltage level prior to time t1. At time t1, the EANVM cell 32is selected and, if the cell 32 is in the erased or tilt state, the cell32 provides a low impedance path to ground. As a result, the bit line ispulled down to near the ground potential provided at terminal 36 in FIG.2. If the EANVM cell 32 were in the “0” or fully programmed state, thebit line voltage would remain at the Vpull-up voltage after time t1. Thevoltage on the bit-line terminal 38 and the reference voltage Vref atterminal 43 are compared by the comparator 42, whose buffered outputdrives I/O terminal 50. When Vref is greater than the bit line voltage,the output on I/O terminal 50 is a logical “0”. When Vref is lower thanthe bit line voltage, the output on I/O terminal 50 is a logical “0”.

[0050] II. MEMORY ARRAY FOR A MULTI-BIT EANVM SYSTEM

[0051]FIG. 5 is a block diagram of a multi-bit per cell EANVM system 100which includes an M×N array of memory cells. The cells are typicallyshown as a floating gate FET, or EANVM, 102, as described in FIG. 1. Thearray uses similar addressing techniques, external control signals, andI/O circuits as are used with currently available single bit per cellEANVM devices such as EPROM, EEPROM, FLASH, etc. devices. Row Addresssignals are provided at input terminals 103A and Column Address signalsare provided at input terminals 103B.

[0052] Each of the EANVM cells in a row of cells has its sourceconnected to a ground reference potential and its drain connected to acolumn bit line, typically shown as 106. Each of the columns isconnected to a pull-up device, as indicated by the block 105. All of thecontrol gates of a row are connected to a row select, or word, line,typically shown as 104. Rows are selected with a row select circuit 108and columns are selected with a column select circuit 110. Senseamplifiers 112 are provided for each of the selected columns.Decode/encode circuits 114 and n-bit input/output latches/buffers 116are also provided. A PGM/Write signal is provided at an input terminal118 for activating a mode control circuit 120 and a timing circuit 122.

[0053] A significant feature of this n-bit per cell system 100 ascompared to a single-bit per cell implementation is that the memorydensity is increased by a factor of n, where n is the number of bitswhich can be stored on an individual multi-bit memory cell.

[0054] III. BASIC READ MODE OF AN N-BIT MEMORY CELL

[0055]FIG. 6 shows a binary system 150 for reading the state of an n-bitfloating gate memory cell 102, as described in FIG. 1, according to theinvention, where n is the number of bits stored in the memory cell. Forthis example, n is set to 2 and one of four states of the memory cellmust be detected. The four possible states being, (0,0), (0,1), (1,0),or (1,1). Detecting which state is programmed-requires a 4-level senseamplifier 152. This amplifier includes three sense amplifiers 154, 156,158 each of which have their negative input terminals connected to theoutput terminal 106 of the memory cell 102. Sense amplifier 154 has areference voltage Ref 3 connected to its positive input terminal. Senseamplifier 156 has a reference voltage Ref 2 connected to its positiveinput terminal. Sense amplifier 158 has a reference voltage Ref 1connected to its positive input terminal. The voltage references are setsuch as follows: Vpull-up>Ref 3>Ref 2>Ref 1. The respective outputsignals S3, S2, S1 of the three sense amplifiers drive an encode logiccircuit 160, which encodes the sensed signals S3, S2, S1 into anappropriate 2-bit data format. Bit 0 is provided at an I/O terminal 162and Bit 1 is provided at an I/O terminal 164. A truth table for theencode logic circuit 160 is as follows: S3 S2 S1 I/0 1 I/0 0 State L L L0 0 (0,0) H L L 1 0 (1,0) H H L 0 1 (0,1) H H H 1 1 (1,1)

[0056] During a read operation of an n-bit memory cell, the levels ofthe respective output signals S3, S2, S1 of the sense amplifiers 154,156, 158 are determined by the conductivity value to which the memorycell had been set during a programming operation. A fully erased EANVMcell 102 will be in its lowest threshold voltage state, or the highestconductivity state. Consequently, all of the reference voltages will behigher in voltage than the bit line voltage at terminal 106, resultingin a (1,1) state. A fully programmed EANVM cell 102 will be in itshighest threshold voltage state, or its lowest conductivity state.Consequently, all reference voltages will be lower in voltage than thebit line voltage at terminal 106, resulting in a (0,0) state. Theintermediate threshold states are encoded as is illustrated in the truthtable for the logic circuit 160. FIG. 7 shows the bit line voltage as afunction of time at terminal 106, during a read cycle, for a binary2-bit per memory cell. For purposes of illustration, each of the fourpossible waveforms corresponding to the four possible programmed statesof the memory cell are shown. During a read cycle only the waveformcorresponding to the programmed state of the EANVM cell would occur. Forexample, 25 assume the EANVM memory cell 102 has been programmed to a(1,0) state. Prior to time t1, because the EANVM cell 102 has not yetbeen selected or activated, the bit line 106 is pulled-up to Vpull-up.At time t1, 22 the EANVM cell is selected using conventional memoryaddress decoding techniques. Because the EANVM cell has been programmedto a specific conductivity level by the charge on the floating gate, thebit line is pulled down to a specific voltage level corresponding to theamount of current that the cell can sink at this specific conductivitylevel. When this point is reached at time t2 the hit line voltagestabilizes at a voltage level Vref2 between reference voltages Ref 3 andRef 2 which.correspond to a (1,0) state. When the EANVM cell 102 isde-selected, the bit line voltage will return to its pulled-upcondition. Similarly, the bit-line voltage stabilizes at Vref1 for the0,1 state for the other specific conductivity levels, or at zero voltsfor the 1,1 state. FIG. 8 is a block diagram of an n-bit memory cellsystem 200. For purposes of illustration a binary 2-20 bit per cellsystem is shown. However, it is intended that the concepts of theinvention extend to systems where n is greater than 2. It is alsointended that the invention include any system where the EANVM memorycell has more than two states. For example, in a non-binary system, thememory states can be three or some other multiple of a non-binarysystem. Some of the components of this system 200 are shown anddescribed with the same reference numerals for the components of FIG. 6for the read mode of operation. It is intended that these same referencenumerals identify the same components.; The system 200 includes a memorycell 102, as described in FIG. 1, with a bit line output terminal 106.For the read mode of operation, a 4-level sense amplifier 152 with readreference voltages Ref 1, Ref 2, and Ref 3 and an encoder 160 isprovided. Read data is provided at a Bit I/O terminal 162 and at a Bit II/0 terminal 164. For the write mode of operation, a verify referencevoltage select circuit 222 provides an analog voltage reference levelsignal X to one input terminal of the analog comparator 202. The verifyreference voltages are chosen so that as soon as the bit line voltage onbit line 106 is greater than the verify reference voltage the thresholdof the EANVM cell 102 is set to the proper threshold corresponding tothe memory state to which it is to be programmed. To this end the verifyreference voltages Vref1, Vref2, Vref3, and Vref4 are set such thatVref4 is above Ref 3, Vref3 is between Ref 3 and Ref 2, Vref2 is betweenRef 1 and Ref 2, and Vref1 is below Ref 1. During a normal readoperation, the bit line voltage will settle midway between the readreference voltages to insure that the memory contents will be readaccurately. The verify reference voltage select circuit 222 iscontrolled by the 2-output bits from a 2-bit input latch/buffer circuit224, which receives binary input bits from the I/O terminals 162 and164. The Y signal input terminal of the analog comparator 5202 isconnected to the bit line output terminal 106 of the multi-level memorycell 102. The output signal from the analog comparator is provided on asignal line 204 as an enable/disable signal for the program voltageswitch 220. An output signal line 206 from the program voltage switch220 provides the word line program voltage to the control gate of theEANVM cell 102. Another output signal line 206 provides the bit-lineprogramming voltage to the bit-line terminal 106 of EANVM cell 102.After the program/verify timing circuit 208 is enabled by a PGM/Writesignal provided on signal line 212 from a PGM/Write terminal 214, thetiming circuit 208 provides a series of program/verify timing pulses tothe program voltage switch 220 on a signal line 210. The pulse widthsare set to control the programming process so that the voltage thresholdof the EANVM cell 102 is incrementally altered by controlling theinjection of charge onto the floating gate of the EANVM cell. Eachprogramming cycle increases the voltage threshold and, as a result,decreases the conductance of the memory cell 102. After each internalprogram cycle is complete, as indicated by signal line 210 going “high”,the program voltages are removed via the Program Voltage Switch 220 anda verify cycle begins. The voltage threshold of memory cell 102 is thendetermined by using the comparator 202 to compare the bit line voltageat terminal 106 with the selected verify reference voltage from theverify reference voltage select circuit 222. When the bit line voltageexceeds that supplied by the verify reference voltage select circuit222, the output signal 204 from the comparator 202 will then disable theprogram voltage switch 220 ending the programming cycle. For thisembodiment of the invention, during a write operation, comparison of thecurrent memory cell analog contents with the analog information to beprogrammed on the memory cell 102 is performed by the analog comparator202. The verify reference voltage select circuit 222 analog outputvoltage X is determined by decoding the output of the n-bit inputlatch/buffer 224. The Y input signal to the analog comparator 202 istaken directly from the bit line terminal 106. Note that the 4-levelsense/encode circuits 152, 160, and reference voltage select circuit 222may be completely independent, as indicated in the drawing.Alternatively, they may be coupled together to alternately time sharecommon circuit components. This is possible because the 4-levelsense/encode circuits 152 and 160 are used in the read mode of operationwhile the verify reference voltage select circuit 222 is used only inthe write/verify mode of operation.

[0057] IV. BASIC WRITE MODE FOR A MULTI-BIT PER CELL EANVM SYSTEM

[0058] In the write mode, a binary n-bit per cell EANVM system must becapable of electrically programming a memory cell to 2^(n) uniquelydifferent threshold levels. In the two-bit per cell implementation,because it is assumed that the cell starts from the erased (1,1) state,it is only necessary to program three different thresholds (Vt1, Vt2,and Vt3) which define the (0,1), (1,0), and (0,0) states. Vt1 is thethreshold required such that in the read mode, the bit line voltage willfall between Ref 1 and Ref 2. Vt2 is the threshold required such that inthe read mode, the bit line voltage will fall between Ref 2 and Ref 3.Vt3 is the threshold required such that in the read mode, the bit linevoltage will be greater than Ref 3.

[0059]FIG. 9 illustrates the change in voltage threshold for a 4-level,or 2-bit EANVM cell as the floating gate is being charged from an erased(1,1) threshold state to any one of the three other possible states. Inprior art single-bit memory cells where there are only two states, thedesign objective is to provide enough charge to the floating gate toinsure that the cell's voltage threshold is programmed as high aspossible, as shown in FIG. 3. Because there is no upper threshold limitin a single-bit per cell system, overprogramming the cell will not causeincorrect data to be stored on the memory cell.

[0060] As illustrated by FIG. 9, in an n-bit per cell system the memorycell must be charged to a point so that the voltage threshold is withina specific voltage threshold range. In this example, where the cell isbeing programmed to a (1,0) state, the proper threshold range is definedas being above a threshold level Vt2 and as being below a thresholdlevel Vt3.

[0061] To accomplish this n-level programming it is necessary to add toor modify the prior art EANVM circuitry. FIG. 8 shows the additional ormodified circuits, including a reference voltage select, an n-bitlatch/buffer, a program/verify timing circuit, and a comparator. Thecomparator can be either digital or analog.

[0062]FIG. 10 illustrates the voltage threshold of an EANVM cell as thefloating gate is being erased from a (0,0) state. Standard EANVMprogramming operating procedure calls for a memory cell to be erasedprior to being programmed. This erasure can be performed at the byte,block, or chip level and can be performed by electrical, UV, or othermeans. In this type of system the cell would be completely erased to a(1,1) state prior to initiating a programming cycle. If a system has thecapability to erase an individual memory cell, then it is not necessaryto erase all of the cells of a group prior to initiating a programmingoperation. It is then possible to incrementally erase an individualmemory cell, as necessary, to program the cell to the appropriatevoltage threshold as is indicated by the waveforms labelled (1,0) and(0,1).

[0063]FIG. 11 is a timing diagram which illustrates how a 2-bit EANVMcell of FIG. 8 is programmed from an erased (1,1) state to a (1,0) stateusing the timing circuitry 208 to generate fixed length timing pulses. Alow logic level state of the PGM/Write signal on signal line 212 enablesthe timing circuit 208. When enabled at time t1, the timing circuit 208provides an internal fixed-width low level internal PGM timing pulse onsignal line 210 to the program voltage switch 220. For the duration ofthe low state of the internal PGM timing pulse, the bit line and wordline program voltage outputs on lines 216 and 206 will be raised totheir respective programming voltage levels as shown in FIG. 11. Duringthis programming process, charge is added to the floating gate of thememory cell 102. When the internal PGM timing pulse from timingcircuitry 208 switches to a high level, the programming voltages areremoved and a verify cycle begins. For this example, verify referencevoltage Vref3 is compared with the bit line voltage. This internallycontrolled program/verify cycle repeats itself until the bit linevoltage on terminal 106 exceeds Vref3. At this time, t2, the EANVM cell102 is verified to have been programmed to a (1,0) state and programmingis halted by the comparator 222 providing a disable signal on signalline 204 to the program voltage switch 220.

[0064]FIG. 12 illustrates the bit line voltage of a 2-bit per cell EANVMas it is being programmed from a fully erased, or fully “on”, state(1,1) to a partially “off”state (1, 0) using fixed length programpulses. When the externally applied PGM/Write pulse is applied at timet1, the program/verify timing circuit 208 first initiates a verify cycleto determine the current status of the memory cell 102. This isindicated by the bit line voltage being pulled to a ground conditionfrom, in this example, Vpull-up. Although, prior to time t1, the bitline voltage could be pre-set to any voltage level. Once the cell hasbeen determined to be at a condition below the verify reference voltage,Vref3 in this example, corresponding to the data to be programmed, thefirst program cycle is initiated. This is represented by the bit linevoltage being pulled up to Vprogram. After the first fixed lengthprogramming pulse ends, a verify cycle begins. This is represented bythe bit line voltage being pulled down to a point midway between groundpotential and Ref1. During each successive verify cycle the bit linevoltage is observed to incrementally increase. This program/verify cyclecontinues until the bit-line voltage exceeds the selected verifyreference voltage, in this case Vref3, which indicates a memory state of(1,0), at time t2.

[0065]FIG. 13 illustrates how a 2-bit EANVM cell is programmed from anerased (1,1) state to a (1,0) state using variable length programmingpulses. The internal PGM pulses for this implementation start with a lowstate longer than for fixed-width implementation of FIGS. 11 and 12. Thelow-state pulse widths grow progressively shorter as the memory cellapproaches the appropriate voltage threshold. This approach requiresmore precise control than the fixed length approach. However,programming times can be greatly reduced on average.

[0066]FIG. 14 illustrates the bit line voltage of a 2-bit per cell EANVMas it is being programmed from a fully erased, or fully “on”, state(1,1) to a partially “off”state (1,0) using variable length programpulses. When the externally applied PGM/Write pulse goes to an activelow level at time t1, the program/verify timing circuit 208 firstinitiates a verify cycle to determine the current status of the memorycell 102. This is indicated by the bit line voltage being pulled to aground condition from, in this example, Vpull-up. Although, prior totime t1, the bit line voltage could be pre-set to any voltage level.Once the cell has been determined to be at a condition below the verifyreference voltage corresponding to the data to be programmed, Vref3 inthis example, the first program cycle is initiated. This is representedby the bit line voltage being pulled up to Vprogram. After the firstvariable length programming pulse is over, another verify cycle begins.This is represented by the bit line voltage being pulled down to a pointmidway between Ref1 and Ref2. During each successive verify cycle thebit line voltage is observed to incrementally increase. Thisprogram/verify cycle continues until the bit-line-voltage surpasses theselected verify reference voltage, in this case vref3 which indicates amemory state of (1,0), at time t2.

[0067] Accordingly, the programming process for an n-bit per cell EANVMuses program/verify cycles, to incrementally program a cell. Theduration of these cycles are determined by the timing circuit 208. A keyelement of the system is to provide a programming scheme which providesfor accurate programming of the memory cell 102. This is accomplished bymatching the pulse widths of the timing pulses of the timing circuitry208 to the program time of the EANVM cell being used. As indicated inFIGS. 11 and 13, a desired voltage threshold actually falls within arange of threshold voltages. If the program pulses are too long, thentoo much charge may be added to the floating gate of the memory cell102. This may result in an overshoot of the target voltage threshold,resulting in incorrect data being stored in the memory cell.

[0068] The programming pulse width is set such that if the voltagethreshold of the cell 102 after the (n−1) programming pulse is at apoint just below the target voltage threshold, then the (n)th, or final,program pulse will not cause an overshoot resulting in an overprogrammedcondition for a memory cell.

[0069]FIG. 8 may also use a digital comparator rather than the analogcomparator 202 shown in FIG. 8. The digital comparator would use theencoded data from the encode circuitry 160 as the input to thecomparator represent the current contents of the EANVM cell 102. Theverify reference voltage select 222 would provide the voltage to beencoded with the input coming from the output of the n-bit inputlatch/buffer 224, representing the data to be programmed. Otherwise, thefunction of the comparator within the system remains the same.

[0070] V. EMBODIMENTS TO ESTABLISH REFERENCE VOLTAGES

[0071] A multi-level (or multi-bit) memory device which contains morethan one bit of information per memory cell needs accurate and stablereference voltages. The reference voltages allow a multi-level memorycell to be correctly read over various process, voltage, and temperatureranges. The reference voltages must be implemented into the integratedcircuit which can accurately sense the multi-level voltage levels of thememory cells as well as track each memory array voltage level as itdrifts with the process, voltage, and temperature variations. Anunstable or inaccurate reference voltage tends to cause problems such asan improper voltage level read of a bit line, and the like from a memorycell.

[0072] In a 2-bit per memory cell embodiment, the memory cell includesfour voltage levels V0, V1, V2, and V3 at each of the bit lines asillustrated by FIG. 15. To uniquely detect each of the four voltagelevels, it is necessary to generate at least three reference voltages,each of the reference voltages falling between memory bit line voltagelevels. When V0, V1, V2, and V3 represent the four bit line voltagelevels, the reference voltages VREF0, VREF1, AND VREF2 fall between V0and V1, V1 and V2, and V2 and V3, respectively. Preferably, thereference voltages-VREF0, VREF1, and VREF2 fall halfway between V0 andV1, V1 and V2, and V2 and V3, respectively. Each reference voltage isalso set to provide a clear and accurate reference level, which can beused as a reference for the bit line voltage.

[0073] In a specific embodiment, a method for establishing referencevoltages for a non-volatile multi-bit memory array is provided. Merelyby way of example, the present method is applied to the manufacture of anon-volatile multi-bit memory array such as a masked ROM array, an EANVMmemory array, and the like. The present method calls for referencevoltage sources and in particular reference voltage lines and cellswhich are fabricated simultaneously with the standard memory cell array.Alternatively, the present method may call for reference voltage sourcesand in particular reference voltage lines and cells which are fabricatedby way of the same method (but at a different step) as the standardmemory cell array. By way of the present method, stable referencevoltages are established which track bit line voltages in memory cellsthrough voltage, temperature, and process variations.

[0074] In a masked ROM embodiment, for example, the present method callsfor reference voltages to be generated using memory cells which havebeen programmed in the same fashion and preferably in exactly the samefashion as the cells in the standard memory array itself. In the presentmasked ROM embodiment whose memory cells are programmed using a Vtimplant, the memory cells within the reference voltage generator circuitwill be implanted at the same time with preferably the same implantdosage as the ROM cells within the standard memory array. This means theimplant dosage of the reference voltage cell is substantially the sameas the memory cell for the bit line in the standard memory array. Thereference voltage level is also substantially the same as the bit linevoltage level, that is, assuming the same voltage is applied to both thereference voltage cell and the bit line cell. As show in FIG. 16 forexample, memory cells within the reference voltage generator circuitinclude field effect transistors 1103, 1104, 1105, 1106, 1107, and 1108.A ROM cell in a memory array may include transistor 1102 coupled to abit line.

[0075] In the present embodiment, the reference voltage is moved to avoltage point away from the bit line voltage. This allows the multi-bitmemory device to sense the relative voltage difference between the bitline and the reference voltage line, and then decode the programmed cellaccordingly. By way of the same implant step, the reference voltagetracks the bit line voltage over process, voltage, and temperaturevariations, and is therefore stable.

[0076] In the present invention, a selected voltage difference existsbetween the voltage reference levels and memory bit line voltage levelssuch that they do not interfere with each other. The voltage referenceand sensing circuitry are able to detect a single unique voltage levelout of four possible levels, in a 2-bit per memory cell configurationfor example. Referring to FIG. 15, if VREF0 was inadvertently raised tothe level of VREF1, a non-programmed memory state of (1,1) is easy read.Unfortunately, if the memory cell was programmed to an intermediatestate of (1,0), the relation between VREF0 to VREF1 makes it difficultto differentiate between the two levels. As a result, the output isoften unreliable and the like. Accordingly, the present invention reliesupon either a voltage divider arrangement, a pull-up device arrangement,or the like, and combinations thereof to create desired referencevoltage levels. Although the present invention is described in themasked ROM embodiment, the present invention may also be applied to anymulti-bit memory array such as an EANVM memory array, and the like.

[0077]FIG. 16 is a simplified reference voltage generator circuit in avoltage divider arrangement 1200 for generating multiple referencevoltages according to the present invention. In a 2-bit per cellembodiment, a multi-level memory cell includes at least four bit linevoltage levels V0, V2, V3, and V4. Each of the four bit line voltagelevels is detected by way of three reference voltage levels, each ofwhich falls between two adjacent bit line voltage levels. The voltagedivider arrangement includes a VREF0 column 1204, a VREF1 column 1206,and a VREF2 column 1208. Each column includes at least a pull-up voltageVPULLUP. A bit line column 1202 is also shown for illustrative purposes.The bit line column is a portion of the standard memory cell array. Asnoted above, the bit line produces a voltage at either V0, V1, V2, orV3, depending upon the particular application. A plurality of rows 1212,1214 (or SELECT lines) are also shown. The SELECT line 1212 includes aplurality of field effect transistors 1109, and the SELECT line 1214includes a plurality of field effect transistors 1101. Each of thecolumns also includes a WORD line 1216 operably coupled to each columnthrough field effect transistors 1102, 1103, 1104, 1106, 1107, and 1108.The field effect transistors 1102, 1103, 1104, 1106, 1107, and 1108include a source/drain region at V, V0, V1, V1, V2, V2, V3,respectively. The field effect transistors may include an NMOS device, aPMOS device, and the like.

[0078] As shown, each pair V0 and V1, V1 and V2, and V2 and V3 connecttogether with a voltage divider arrangement to generate intermediatereference voltages VREF0, VREF1, and VREF2, respectively. By way of thefield effect transistors 1103, 1104, and application of voltage at theWORD line and the SELECT line 1212, the reference voltage VREF0 is at avoltage level between about V0 and about V1. By way of application ofvoltage at the WORD line and SELECT line 1212, the reference voltageVREF1 is between about V1 and about V2. Similarly, by way of applicationof voltage at the WORD line and the SELECT line 1212, the referencevoltage VREF2 is between about V2 and about V3.

[0079]FIG. 17 illustrates the reference voltage levels of for exampleFIG. 16 according to the present invention. The voltage dividerarrangement defines the reference voltages as follows:VREF0 = (V0 + V1)/2 VREF1 = (V1 + V2)/2 VREF2 = (V2 + V3)/2

[0080] The reference voltages VREF0, VREF1, and VREF2 fall between V0and V1, V1 and V2, and V2 and V3, respectively. Accordingly, the presentmulti-bit memory device provides reference voltages which do not overlapwith the bit line voltages. In addition, the references voltages VREF0,VREF1, and VREF2 track well with the memory bit lines over process,voltage, and temperature variations. Preferably, each of the referencevoltages fall exactly halfway between adjacent bit line voltage levels.

[0081]FIG. 18 is a simplified voltage generator circuit diagram 1400 ofan array showing reference voltage columns connected to pull-up devicesaccording to the present invention. Each of the pull-up devices is afield effect transistor such as an NMOS device, a PMOS device, and thelike. Preferably, the pull-up device is a PMOS device. A bit line column2002 is also shown for illustrative purposes. The bit line column is aportion of the standard memory cell array. As noted above, the bit lineproduces a voltage at either V0, V1, V2, or V3, depending upon theparticular application. The bit line also includes a field effecttransistor 1102 and a word line 2016 operably coupled to the fieldeffect transistor.

[0082] The voltage generator circuit includes a plurality of referencevoltage column lines 2004, 2006, 2008, each at the same voltage level onone end VPULLUP, a plurality of field effect transistors 1101, 1109, anda reference voltage at the other end VREF0, VREF1, and VREF2. Betweenfield effect transistors 1101, 1109 are cells which include field effecttransistors 1103, 1105, and 1107. The field effect transistors 1103,1105, and 1107 include source/drain regions coupled to V0, V1, and V2,and source/drain regions coupled to column lines 2004, 2006, and 2008,respectively. A WORD line connects in parallel to each of the fieldeffect transistor (1103, 1105, and 1107) gates. A plurality of SELECTlines 2012, 2014 connect to the transistor (1109, 1101) gates. The bitline and reference voltage lines include pull-up devices 1110, 1111,1112, and 1113, respectively. The pull-up devices create the referencevoltage levels and memory bit line voltage level for sensingmulti-levels on the memory bit line.

[0083] The pull-up devices are defined on the reference voltage lines. Apull-up device is also defined on the bit lines in the memory array. Thedesired reference voltages VREF0, VREF1, and VREF2 can be made bymodifying the size and/or number of pull-ups such as field effecttransistors and the like. The reference voltages are preferably atvoltage levels corresponding to ones illustrated by FIG. 16 for example.Preferably, the pull-ups are added at the point where reference signals(corresponding to reference voltages) feed directly into a senseamplifier circuit, and not on each bit line. Determining the appropriatepull-up device size can occur on a trial and error basis during thecourse of circuit simulation. Other types of pull-up devices orcircuitry such as capacitor and resistor combinations, and the like mayalso be used. Of course, the type of pull-up device and itsconfiguration depend upon the particular application.

[0084] The embodiment of FIG. 18 generally provides a wider voltagerange, than the embodiment of FIG. 17. The circuit for each referencevoltage is no longer substantially dependent upon a maximum voltagerange on the bit line. The effective voltage range can be scaled upacross a wider range through use of selected pull-up devices. Thisprovides for a greater margin of manufacture by the wider range betweenthe voltages. The increased voltage range insures that an adequatesignal is available to sense the difference between the memory bit linevoltage and that of the reference voltage. As previously noted, thepull-up device is preferably a PMOS device and the like.

[0085]FIG. 19 is a simplified voltage generator circuit diagram 1600 forobtaining reference voltages with use of pull-up devices and a voltagedivider according to a preferred embodiment of the present invention. Abit line column 1602 is also shown for illustrative purposes. The bitline column is a portion of the standard memory cell array. As notedabove, the bit line produces a voltage at either V0, V1, V2, or V3,depending upon the particular application. The bit line also includes afield effect transistor 1102 and a word line 1616 operably coupled tothe field effect transistor.

[0086] The voltage generator circuit diagram includes a plurality ofreference voltage columns 1111, 1112, 1113, a plurality of field effecttransistors 1612, 1614 coupled to SELECT lines, and a plurality of fieldeffect transistors 1103, 1104, 1105, 1106, 1107, 1108 in each cellcoupled to a WORD line 1616. Also shown are a plurality of pull-updevices 1111, 1112, and 1113 for a VREF0 line 1604, a VREF1 line 1606,and a VREF2 line 1608, respectively. The embodiment provides for avoltage divider arrangement such that each reference voltage tracks thebit line voltage in variations to process, temperature, voltage, and thelike. In addition, the embodiment provides for each of the referencevoltages VREF0, VREF1, and VREF2 to be conditioned by way of respectivepull-up devices. A pull-up device 1110 may also condition the voltage atthe bit line 1602.

[0087]FIG. 20 illustrates a simplified reference voltage generatorcircuit diagram 2000 according to the present invention. A bit line 2009with four memory cells 2001, 2003, 2005, and 2007, each of which isprogrammed to one of four different threshold voltages (V0, V1, V2, V3)representing the possible states in a two bit per cell memory array isshown for illustrative purposes. The bit line is operable coupledthrough field effect transistors in the memory cells 2001, 2003, 2005,and 2007. The bit line also includes a select line, and word lines 0, 1,2, and 3.

[0088] The reference voltage generator circuit includes referencevoltage lines 2013, 2015, and 2017, for VREF0, VREF1, and VREF2,respectively. The reference voltage generator circuit includes cells2019 which define a reference voltage array 2021. The reference voltagearray includes bit lines 2023 (or reference voltage lines 2013, 2015,and 2017) which were preferably identical in fabrication to the bitlines such as the bit line 2009 in the memory array. For example, thebit lines 2023 in the reference voltage array and the memory array aremade by way of the same (or similar) processing steps.

[0089] The cells 2019 in the reference voltage array are programmed toone of four possible voltage thresholds V0, V1, V2, and V3. Optionally,the bit line in the reference voltage array which contains cellsprogrammed to the highest threshold voltage V3 may be omitted, as cellsprogrammed to a voltage threshold higher than the voltage on the wordline will effectively be an open circuit. This memory bit line in thereference voltage array may be replaced by a voltage source, typicallyrepresenting the highest voltage potential used in the particularintegrated circuit.

[0090] In the present embodiment, the cell (or cells 2001, is 2003,2005, and 2007) in the memory array is programmed by way of a selectedthreshold voltage such as V0 and the like. All of the cells in thereference voltage array using the same threshold voltage is preferablyprogrammed at the same time (or the same method) as the cell (or cells)in the memory array. For example, a cell(s) 2001 at a threshold voltageof V0 in the memory array is programmed by way of implant or the like atthe same step as the cells 2025 at a threshold voltage of V0 in thereference voltage array. The cell(s) 2003 at a threshold voltage of V1in the memory array is programmed by way of implant or the like at thesame step as the cells 2027 at a threshold voltage of V1 in thereference voltage array. The cell(s) 2005 at a threshold voltage of V2in the memory array is programmed by way of implant or the like at thesame step as the cells 2029 at a threshold voltage of V2 in thereference voltage array. Other threshold voltages 2007 may be programmedinto the cells by way of similar programming techniques and the like.The selected programming technique may include a single thresholdvoltage implant or multiple threshold voltage implants corresponding toa series programming steps. An example of such programming step can beany suitable technique known in the art.

[0091] The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the Claims appended hereto and theirequivalents.

The invention claimed is:
 1. For an electrically alterable non-volatilemulti-level memory device including a plurality of non-volatilemulti-level memory cells, each of the multi-level memory cells includinga floating gate FET having a channel with electrically alterable voltagethreshold value, electrons being capable of being injected into thefloating gate, a method of operating the electrically alterablenon-volatile multi-level memory device, comprising: settling a voltagethreshold value of at least one non-volatile multi-level memory cell ofthe plurality of non-volatile multi-level memory cells to one stateselected from a plurality of states including at least a first state, asecond state, a third state and a fourth state in response toinformation to be stored in the one non-volatile multi-level memorycell, and reading status of the one non-volatile multi-level memory cellfrom an output from a bit line coupled to a drain terminal of the onenon-volatile multi-level memory cell, wherein the operation for settlingthe voltage threshold value of the one non-volatile multi-level memorycell includes a program operation, in which electrons are injected intothe floating gate of the one non-volatile multi-level memory cell byapplying at least one programming pulse supplied to the bit line, andwherein the program operation of the one non-volatile multi-level memorycell is carried out by a plurality of programming pulses, the pluralityof programming pulses includes at least a first programming pulse and asecond programming pulse after the first programming pulse, the firstprogramming pulse has a first electric parameter and the secondprogramming pulse has a second electric parameter so that a firstvoltage threshold value change of the one non-volatile multi-levelmemory cell between after applying the first programming pulse andbefore applying the first programming pulse is substantially larger thana second voltage threshold value change of the one non-volatilemulti-level memory cell between after applying the second programmingpulse and before applying the second programming pulse.